1. Technical Field
The present disclosure relates generally to interconnect structures formed in semiconductor devices. In particular, the present disclosure relates to a structure and methods of forming interconnect structures with improved metal caps.
2. Description of Related Art
Integrated circuit chips typically include two or more levels of conductive lines which are vertically spaced apart and separated by intermediate insulating layers. Interconnections are formed between the levels of conductive lines in the chip for providing, for example, high wiring density and good thermal performance. The interconnections are formed by means of lines and vias which are etched through the insulating layers separating the levels. The lines and vias are then filled with a metal (e.g. Cu) to form interconnect elements (i.e. via studs). A typical interconnect element includes metal vias running perpendicular to the semiconductor substrate and metal lines running parallel to the semiconductor substrate. This process results in multiple levels of conductor wiring interconnection patterns, having individual levels connected by via studs and operating to distribute signals among the various circuits on the chip.
Reliability concerns, such as electromigration, constitute a major and persistent difficulty encountered during interconnection formation. In particular, electromigration decreases the reliability of integrated circuits leading, for example, to the eventual loss of one or more connections and intermittent failure of the entire circuit. The electromigration concept is illustrated in FIGS. 1A-1D.
With reference to FIG. 1A, a semiconductor structure 10 is illustrated having a conventional metal interconnect structure 12 formed in insulating materials 14a, 14b and 14c. Dielectric caps 16a and 16b separate insulating material 14a, 14b and 14c from one another. Interconnect structure 12 includes a conductive metal such as Cu. Initially, (time t=0), a conductive electron 18 moves through diffusing Cu atoms. With reference to FIG. 1B, some of the momentum of moving electron 18 is transferred to an activated Cu ion causing the ion to move from its original position. Overtime (time t=1), this momentum causes enough Cu ions to move far enough from their original positions, thus forming void 20 in a top portion of interconnect structure 12. In FIG. 1C, at time t=2, void 20 nucleate causing growth toward the bottom of interconnect structure 12. With reference to FIG. 1D, overtime (at time t=3) this force knocks enough Cu atoms far enough from their original positions permitting void 20 to continue to grow until it crosses the metal interconnect 12 and develops a break or void 20a in interconnect structure 12, thus causing an open circuit.
As the structure size in integrated circuits decreases, the practical significance of the effect of electromigration increases. That is, with increasing miniaturization, the probability of failure due to electromigration increases in very-large-scale integration (VLSI) and ultra-large-scale integration (ULSI) circuits because both the power density and the current density increase in these applications. In fact, electromigration has long been identified as the major metal failure mechanism. Electromigration not only needs to be overcome during the process development period in order to qualify the process, but it also persist through the life time of the chip.
Several solutions to the problems caused by electromigration have been proposed in advanced semiconductor manufacturing processes. For example, copper (Cu) has replaced aluminium as the interconnect material of choice because, despite its greater fragility in the fabrication process, it possesses superior conductivity and is intrinsically less susceptible to electromigration. In addition, it has been demonstrated that replacing the Cu/dielectric interface with Cu/metal interface can enhance the electromigration resistance by more than 100 times. Thus, metal cap is generally preferred over conventional dielectric cap for better electromigration resistance.
FIG. 2A illustrate a prior art interconnect structure having a dielectric cap on the wiring structures. In particular, FIG. 2A describes an interconnect structure 50 including a dielectric material 52 having conductive features 51A, 51B and 51C embedded therein. The conductive features 51A, 51B and 51C include a conductive metal, such as Cu 54 which is located within an opening provided in the dielectric material 52. The Cu 54 is separated from the dielectric material 52 by a diffusion barrier 56. A dielectric capping layer 58 is deposited on the upper exposed surface of each conductive feature (i.e., Cu 54) during a deposition process. Typically, capping layer 58 includes Si3N4, SiC or SiC(N,H). As discussed and shown in FIGS. 1A-1D, the Cu 54/dielectric 58 interface is a high electromigration diffusion path, and this interconnect structure containing this Cu/dielectric interface is a reliability concern on electromigration related failures.
FIG. 2B illustrate another prior art from a selective metal cap deposition process on interconnect or wiring structures. In particular, and similarly to FIG. 1, FIG. 2B shows a prior art interconnect structure 50 including a dielectric material 52 having conductive features 51A, 51B and 51C embedded therein. The conductive features 51A, 51B and 51C include a conductive material 54 which is located within an opening provided in the dielectric material 52. The conductive material 54 is separated from the dielectric material 52 by a diffusion barrier 56. A metallic capping layer 60 is deposited on the upper exposed surface of each conductive feature (i.e., conductive material 54) during a selective deposition process. Capping layer 60 may include a selectively deposited metal, such as CoWP resulting on a wiring structure having a Cu/metal interference with superior adhesion strength when compared to the typically used Cu/dielectric interface (illustrated in FIG. 2A) and having enhanced electromigration resistance. Despite the improvement in electromigration resistance, however, the use of metallic capping layer 60 provides an interconnect structure with metallic residue 62 present on the surface of the dielectric material, as illustrated in FIG. 2B. This problematic metallic residue 62 forms during the formation of metallic capping layer 60. The presence of the metallic residue 62 between each of the conductive features hinders or degrades the reliability of the prior art interconnect structure and has delayed using metallic capping layers for the last three generations. In addition, uniformity is very difficult to control when working with multiple chips often resulting in electrical shorts between adjacent interconnects is a concern for selective metal cap application.
FIGS. 3A-3C illustrate yet another proposed method of forming a metal cap in interconnect or wiring structures for enhancing electromigration resistance. In this particular embodiment of the prior art, a metal cap via Cu recess process has been proposed. FIG. 3A illustrates a prior art interconnect structure 70 that includes a dielectric material 72 having a conductive material 74 (i.e. Cu) embedded within via opening 76 provided in the dielectric material 72. A first chemical mechanical planarization (CMP) is conducted following the deposition of conductive material 74. A hardmask layer 78 is deposited prior to forming via opening 76 using conventional lithographic techniques. Conductive material 74 may be separated from the dielectric material 72 by a diffusion barrier (not shown). A wet etching technique by acids including, for example, HF, H2SO4, HCl or H3NO4, is used to remove a top portion of conductive material 74 for forming a recesses region 80, as shown in FIG. 3B. Next, a metallic capping layer 82 is deposited, filling recess region 80. A second CMP is then carried out following the deposition of metallic capping layer 82, resulting in the structure shown in FIG. 3C. In addition to problems of non-uniformity from the mentioned recess process, a high cost is a big concern for manufacturing metal cap via Cu recess process since it involves two CMP processes.
Therefore, a need exist for a novel method of forming metal caps in interconnect structures which overcomes the shortcomings of the prior art and which is compatible with existing integration schemes.